Verilog Coding for Logic Synthesis
-15%
portes grátis
Verilog Coding for Logic Synthesis
Lee, Weng Fook
John Wiley & Sons Inc
05/2003
309
Dura
Inglês
9780471429760
15 a 20 dias
660
Descrição não disponível.
Table of Figures. Table of Examples.
List of Tables.
Preface.
Acknowledgments.
Trademarks.
Introduction.
Asic Design Flow.
Verilog Coding.
Coding Style: Best-Known Method for Synthesis.
Design Example of Programmable Timer.
Design Example of Programmable Logic Block for Peripheral Interface.
List of Tables.
Preface.
Acknowledgments.
Trademarks.
Introduction.
Asic Design Flow.
Verilog Coding.
Coding Style: Best-Known Method for Synthesis.
Design Example of Programmable Timer.
Design Example of Programmable Logic Block for Peripheral Interface.
Este título pertence ao(s) assunto(s) indicados(s). Para ver outros títulos clique no assunto desejado.
ic chip; practical introduction; rapid; synthesizable; change; code; verilog; development; types; language; hardware; currently; two; hdl; industry; description; specifically; practical; logic synthesis; text; simple; examples; design
Table of Figures. Table of Examples.
List of Tables.
Preface.
Acknowledgments.
Trademarks.
Introduction.
Asic Design Flow.
Verilog Coding.
Coding Style: Best-Known Method for Synthesis.
Design Example of Programmable Timer.
Design Example of Programmable Logic Block for Peripheral Interface.
List of Tables.
Preface.
Acknowledgments.
Trademarks.
Introduction.
Asic Design Flow.
Verilog Coding.
Coding Style: Best-Known Method for Synthesis.
Design Example of Programmable Timer.
Design Example of Programmable Logic Block for Peripheral Interface.
Este título pertence ao(s) assunto(s) indicados(s). Para ver outros títulos clique no assunto desejado.
